Priority is claimed from Republic of Korea Patent Application No. 2001-56742 filed Sep. 14, 2001, the entire contents of which are incorporated herein.
The present invention relates to a method for fabricating a semiconductor device. Particularly, the present invention relates to a method for fabricating a semiconductor device, in which a plug is involved.
As semiconductor devices undergo increases in component density and miniaturization, in order to increase speed, the area occupied by capacitors in semiconductor devices is decreased. As semiconductor devices undergo increases in component density and miniaturization, capacitors have to retain minimum values of capacitance.
In order to establish the capacitance of the capacitor, the lower electrode of the capacitor is fabricated in various configurations, such as, cylindrical structures, stacked structures, pin structures, or concave structures. These structures allow the effective area of the lower electrode of the capacitor to be maximized within limited areas.
In another method of establishing the capacitance of the capacitor, materials having a high dielectric constant, such as barium strontium titanate (BST), or Ta2O5, are used in the capacitor. If a dielectric material such as BST or Ta2O5 is used, the upper and lower electrodes of the capacitor are made of platinum (Pt), ruthenium (Ru) or TiN because of considerations of electrical properties.
Particularly, where the lower electrode of the capacitor is fabricated using the metals mentioned above, a transistor including a word line and bit line is formed on a semiconductor substrate, and then, a capacitor contact plug is formed for connecting the capacitor to the transistor. Then a lower electrode is connected to the capacitor contact plug, thereby forming a polysilicon plug (PP) structure. The PP structure is known to be suitable for fabricating a high density semiconductor devices.
FIG. 1 illustrates the layout of a conventional semiconductor device. As shown in FIG. 1, a word line (WL) and a bit line (BL) are formed on a semiconductor substrate 11 in a mutually crossing structure. On a region of semiconductor substrate 11 where the word line and the bit line cross each other, is formed a storage node contact plug (SNC) to which a storage node will be contacted.
FIGS. 2A to 2D are cross-sectional views taken along dashed line A-Axe2x80x2 of FIG. 1 showing the conventional fabricating method for a semiconductor device. Here, a capacitor over bit line (COB) structure is formed.
As shown in FIG. 2A, on semiconductor substrate 11 on which a transistor (not illustrated) including a word line and a source/drain has been formed, there is deposited a first interlayer insulating film 12. Then a flattening process is performed.
Then, first interlayer insulating film 12 is selectively etched to form a contact hole so as to expose a relevant portion (source or drain) of semiconductor substrate 11. Then a first polysilicon plug 13 is buried into the contact hole.
In an alternative method for fabricating first polysilicon plug 13, polysilicon is deposited on the entire surface including the word line, and then, etching is performed in a line pattern. Then, a first interlayer insulating film 12 is deposited, and then chemical-mechanical polishing is performed until a surface of the word line is exposed, thereby completing the process.
Here, first polysilicon plug 13 is the contact plug which will be contacted to the bit line and the storage node contact. In the drawing, there is illustrated only the portion to which the storage node contact is to be contacted.
Next, a second interlayer insulating film 14 is deposited on first interlayer insulating film 12 in which the first polysilicon plug has been buried, and then, a flattening process is performed. Then a plurality of bit lines 15 are formed at certain gaps on second interlayer insulating film 14.
Then, spacers 16 are formed on both of the sidewalls of bit lines 15. A third interlayer insulating film 17 is deposited on the entire surface including bit line 15, and then, a flattening process is performed. A barrier nitride film 18 and a buffer oxide film 19 are then sequentially formed on flattened third interlayer insulating film 17. A storage node contact mask 20 is formed on buffer oxide layer 19 by using a photoresist film.
As shown in FIG. 2B, first buffer oxide film 19 and barrier nitride film 18 are etched using storage node contact mask 20. Third interlayer insulating film 17 and second interlayer insulating film 14 are also etched to form a storage node contact hole 21 to expose the surface of first polysilicon plug 13 between bit lines 15 (referred to as xe2x80x9cself-aligned contactxe2x80x9d below). Then, storage node contact mask 20 is removed.
As shown in FIG. 2C, a polysilicon film is deposited on the entire surface including storage node contact hole 21, and then, the polysilicon film is etched back to form a second polysilicon plug 22 (referred to as xe2x80x9cstorage node contact plugxe2x80x9d below) which is vertically contacted with first polysilicon plug 13.
Then, an oxide film 23 (referred to as xe2x80x9ccapacitor oxide filmxe2x80x9d below), a hard mask 24 and a reflection preventing mask 25 are sequentially deposited on buffer oxide film 20 including storage node contact plug 22. Oxide film 23 determines the height and the shape of the storage node.
A storage node mask (not illustrated) is formed on reflection preventing film 25 by using a photoresist film. Reflection preventing film 25, hard mask 24 and capacitor oxide film 23 are etched by utilizing the storage node mask to form a concave part 26 so as to expose a surface of storage node contact plug 22.
As shown in FIG. 2D, the storage node mask is removed, and then, a storage node 27 is formed only in concave part 26. Prominences, such as meta-stable polysilicon (MPS) 28, are grown.
The process of forming storage node 27 and MPS 28 is performed in the following manner. First, without isolating the cells from each other, MPS 28 is grown on the surface of storage node 27. Storage node 27 is isolated by performing a chemical-mechanical polishing. Or, alternatively, storage node 27 is first isolated, and then, MPS 28 is grown on its surface. Then, a dielectric node 29 and a plate node 30 are sequentially deposited on the entire surface including isolated storage nodes 27.
In the above described conventional technique, the buffer oxide film is also etched during etching of the capacitor oxide film. As show in FIG. 3A, the storage node contact plug protrudes above the barrier nitride film (Section B by about 1000 xc3x85 (refer to the portion B of FIG. 3a). As a result, the area of the storage node is decreased. Particularly as shown in FIG. 3B, if a misalignment occurs during the process of forming the storage node mask, a bridge is formed between the storage node and an adjacent storage node contact plug (Section Bxe2x80x2 of FIG. 3B).
Further, when forming the storage node plug, if a misalignment occurs during the contact mask process, then a current leakage occurs between the bit line and the storage node contact plug. This current leakage affects the yield of the self-aligned contact etching (SAC). Particularly, in the 0.13 xcexcm semiconductor product group, in which a fine wiring width is applied, this phenomenon has more serious consequences.
Further, in the above described conventional technique, the chemical-mechanical polishing (CMP) is performed for isolating the storage node after forming the MPS, and thus, the MPS grains are broken. Further, the broken pieces of the grains are not completely removed during a subsequent wet wash process, and therefore, the broken pieces remain buried within the storage node.
Thus, in the dielectric medium which is deposited by the chemical vapor deposition method (CVD), an increases in the leakage current in the capacitor occurs. An increase in leakage current may also be caused by due a stepped difference cladding of the upper electrode. Further, if the MPS pieces are buried between the storage nodes, then a bridge is formed, thereby generating double-bit defects.
The effects of chemical-mechanical polishing carried out after the formation of the MPS is overcome by the method described herein. That is, the storage nodes are isolated from each other by performing a chemical-mechanical polishing, and then, the MPS is grown on the surface of the storage node.
This method may overcome the breaking of the MPS grains during the chemical-mechanical polishing. However, an MPS seed will be partly grown on the uppermost non-crystalline silicon layer of the storage node (which is the lower electrode) during the growing of the MPS (this will be called xe2x80x9cout-growingxe2x80x9d below). As a result, either the gaps between the storage nodes are narrowed, or in a worst case, bridges are formed between the nodes, thereby generating double-bit defects.
An aspect related to the present invention provides a method for fabricating a semiconductor device in which there can be prevented the formation of bridges between storage nodes and storage node contact plugs and between bit lines and the storage node contact plugs due to a misalignment in the masking process.
Another aspect related to the present invention provides a method for fabricating a capacitor in which MPS growing can be carried out on the uppermost surface of the storage node, and the formation of bridges between the storage nodes during the MPS out-growing can be inhibited.
Another aspect related to the present invention provides a method for fabricating a capacitor in which the reduction of the area of the storage node due to the exposure of the storage node contact plug after an etch of the capacitor oxide film can be inhibited.
In one aspect related to the present invention, a method for fabricating a contact plug according to the present invention includes the steps of forming an insulating film on a semiconductor substrate; selectively etching the insulating film to form a contact hole so as to expose the semiconductor substrate; forming a spacer on a side wall of the contact hole; and plugging a conductive film into the contact hole.
In another aspect of the present invention, a method for fabricating a capacitor according to the present invention includes the steps of forming a first insulating film on a semiconductor substrate, and forming a contact plug through the first insulating film; sequentially forming an etch barrier film and a second insulating film upon the first insulating film; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the contact plug; forming a conductive film on the second insulating film and on the opening part; selectively etching the conductive film, with the conductive film being over-etched relative to the second insulating film, so as to form a storage node within the opening part; forming prominences on a surface of the storage node; and sequentially forming a dielectric film and a plate node upon the storage node.
In still another aspect of the present invention, a method for fabricating a semiconductor device according to the present invention includes the steps of forming a first insulating film on a semiconductor substrate; forming a plurality of bit lines on the first insulating film; forming a contact hole through the first insulating film between the bit lines to reach the semiconductor substrate; forming a spacer on a side wall of the contact hole; forming a first contact plug, the first contact plug being buried into the contact hole to reach the semiconductor substrate; sequentially forming an etch barrier film and a second insulating film on the first insulating film and upon the first contact plug; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug; forming a first conductive film on an entire surface (including the opening part); selectively etching the first conductive film, with the first conductive film being over-etched relative to the second insulating film, so as to form a storage node within the opening part; and sequentially forming a dielectric film and a plate node upon the storage node.
Additional aspects related to the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Certain aspect related to the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.